Panasonic MN103001G/F01K manuals

Owner’s manuals and user’s guides for Computers Panasonic MN103001G/F01K.
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Panasonic MN103001G/F01K User Manual (466 pages)


Brand: Panasonic | Category: Computers | Size: 2.44 MB |

 

Table of contents

MN103001G/F01K

1

LSI User’s Manual

1

Table of Contents

10

7. Internal Memory

11

8. Bus Controller (BC)

11

9. Interrupt Controller

12

10. 8-bit Timers

12

11. 16-bit Timers

13

12. Watchdog Timer

13

13. Serial Interface

13

14. A/D Converter

14

15. I/O Ports

14

16. Internal Flash Memory

15

17. Ordering Mask ROM

15

Appendix

15

List of Figures and Tables

16

List of Tables

23

1. General Specifications

27

1.1 Overview

28

1.2 Features

28

_____________

29

TOP VIEW

31

General Specifications

32

Table 1-4-1 Pin Assignments

32

2.2 Block Diagram

37

2.3 Programming Model

38

LD EXT DROM ROM

42

USE WAIT W WAIT

42

Reset 00000 0000 000 0 00 0

43

2.4 Instructions

44

2.5 Interrupts

48

1413121110987654321

51

3 Cycles

54

Operation extension interface

58

3.2 Extension Instructions

59

Bit 31 Bit 0

60

10000000000000000

83

Dm[31:24]

84

Dm[23:16] Dm[15:8] Dm[7:0]

84

Multiply-and

88

MCRH, MCRL access instruction

89

4. Memory Modes

97

MN103001G

99

/MN1030F01K

99

Memory Modes

102

5. Operating Mode

103

5.1 Overview

104

5.2 Reset Mode

105

5.3 Low Power Mode

106

6. Clock Generator

107

6.1 Overview

108

6.2 Features

108

6.3 Block Diagram

108

6.4 Description of Operation

109

SYSCLK MCLK IOCLK

110

7.1 Overview

112

7.2 Features

112

CPU core

113

Internal Memory

114

8.1 Overview

116

8.2 Features

116

8.3 Bus Configuration

117

8.4 Block Diagram

117

8.5 Pin Functions

119

8.6 Description of Registers

121

Settings other than those

122

CAO (ADE)+CAS (REN)

127

≥ WEN 11111: 31MCLK

127

Reset 1 1 11111111111111

137

31 30 29 28 27 26 25 24 23 22

140

External address (8 MB space)

140

Extension address

140

Bus Controller (BC)

141

Processor mode

141

Extension memory mode

141

8.8 Operation Clocks

142

8.9 Mode Settings

142

4 2 1 1/2

143

Internal Read

143

6 to 9 6 to 9 6 to 9 6

143

8.11 Store Buffer

144

DK detection start

149

Consumed internally

157

Consumed internally by the BC

157

“Description of Registers.”

164

A[0]=1 data outdata outA[0]=0

167

“0”( )“L”

167

“0”(“L”)

168

“0” (“L”)

175

Row Column ColumnRow

178

Refresh count value

183

8.15 Bus Arbitration

184

8.16 Cautions

187

9.1 Overview

190

9.2 Features

190

9.3 System Diagram

190

9.4 Block Diagram

191

Interrupt control

192

9.5 Description of Registers

194

Bit No.1514131211109876543210

198

9.6 Description of Operation

218

Interrupt Controller

220

10.1 Overview

222

10.2 Features

222

10.3 Block Diagram

223

8-bit Timers

224

10.4 Functions

229

10.5 Description of Registers

230

Bit No.76543210

237

Reset 0 0 0 0 0 0 0 0

237

10.6 Description of Operation

240

TMnBR value TMnBR value-1

245

10.6.3 Cascaded Connection

246

TM0BR value

250

TM0BR value-1

250

TM1BR value

250

TM1BR value - 1

250

11.1 Overview

256

11.2 Features

256

11.3 Block Diagram

257

16-bit Timers

258

I/O port block

259

Timer 13

259

Timer 12

259

Timer 11

259

Timer 10

259

(TM10CB)

260

11.4 Functions

261

11.5 Description of Registers

262

TM10CA valueTM10CA value-1

273

TM10CA value-2

273

Pin input

274

(TM10IOA)

274

TM10BC overflow

276

Don' t Care

277

TM10BC value

281

TM10CNE flag

281

Change in the value

283

TMnBR value -1

291

12.1 Overview

294

12.2 Features

294

12.3 Block Diagram

295

12.4 Description of Registers

296

(n + WDCK x 2)

299

Watchdog Timer

300

SYSCLK 255-cycle width

301

13.1 Overview

304

I/O Port Block

307

Interrupt request

313

Bi-directional transfer

316

Undirectional transfer

316

Start sequence resend

325

Serial interface n

327

(n = 1, 2)

327

Serial interface 3

339

Bit No. 7 6 543210

345

Reset 0 0 000000

345

Access RRRRRRRR

345

Serial Interface

349

10-bit sequential

356

Selector

356

14.2 Features

357

14.3 Block Diagram

358

14.4 Description of Registers

359

14.5 Description of Operation

361

■ Operating mode selection

361

Sampling cycle

365

15.1 Overview

368

15.2 Port 0

372

Access R R R R R R/W R/W R/W

373

15.3 Port 1

376

I/O Ports

377

15.4 Port 2

381

15.5 Port 3

385

15.6 Port 4

388

I/O Ports

390

Access R R R/W R/W R/W R R R

393

15.7 Port 5

395

Bit No. 76543210

402

Reset 00111111

402

15.8 Port 6

404

15.9 Port 7

407

Bit name ----P73S - -

409

Access RRRRR/WRRR

409

15.10 Port 8

411

15.11 Port 9

414

Reset 01100000

417

15.12 Port A

419

15.13 Port B

423

15.14 Port C

427

Pin name Treatment

430

16.1 Overview

432

16.2 Features

432

16.3 Block Diagram

432

Internal Flash Memory

435

Internal Flash Memory

436

Table 16-5-2 Pin Functions

436

16.6 On-board Write Mode

438

17.1 Overview

440

Ordering Mask ROM

441

Ordering Mask ROM

442

Appendix-2

444

Appendix-3

445

Appendix-4

446

Appendix-5

447

Appendix B. Instruction Set

447

Appendix-6

448

Appendix-7

449

Appendix-8

450

Appendix-9

451

Appendix-10

452

Appendix-12

454

Appendix-13

455

Corrections

458

Note) n= 0, 1, 2, 3

462

LSI User's Manual

465

SALES OFFICES

466





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