Panasonic MN103001G/F01K User Manual download pdf (Page 138)

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101

Bus Controller (BC)

8-24

8.6.7 Page Row Address Register

Page Row Address Register

Address: x'32000044

Purpose: Sets the row address for DRAM software page mode.

Bit No. 15 14 13 12 11 10 9876543210

Bit PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR

name 15 14 13 12 11 10 9876543210

Reset XXXXXXXXXXXXXXXX

Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

When DRAM software page mode is initiated (i.e., when the PE bit in memory control register 1B/2B is set to “1”),

the contents of the page row address register are output as the row address.

Set the row address in the page row address register before initiating DRAM software page mode. The row address

that is set at this point should have already been subjected to the shift operation in accordance with the DRAM size.

8.6.8 Clock Control Register

Clock Control Register

Address: x'32004000

Purpose: Sets the internal clock multiplier, etc.

Bit No. 15 14 13 12 11 10 9876543210

Bit name

––––––––––––––

MCK MCK

name 10

Reset 0000000000000000

Access RRRRRRRRRRRRRRR/WR/W

Bit No. Bit name Description Setting conditions

1 to 0 MCK1 to 0 MCLK frequency setting for the input frequency 00: 1x

01: 2x

10: 4x

11: prohibited

For details, refer to Chapter 6, “Clock Generator.”

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Panasonic MN103001G/F01K User Manual Page 138

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