Panasonic MN103001G/F01K User Manual download pdf (Page 153)

Bus Controller (BC)

8-39

8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode

8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins,

and for blocks 1 to 3 by setting the BnBW bit to "0" in the corresponding memory control register. In 8-bit bus

mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order

byte and A[0] = "1" for the high-order byte. Word access (32 bits) is performed by means of four accesses, with

A[1:0] = "00", A[1:0] = "01", A[1:0] = "10", and A[1:0] = "11", starting from the low-order side. Note that the low-

order 8 bits (D7 to 0) are used for the data bus.

In synchronous mode, the bus access starts in synchronization with SYSCLK, and when fixed wait states are

inserted, the access ends according to the timing that was set in the memory control register.

The various parameters for external memory access are set in memory control registers 0 to 3, corresponding to

each block.

Fig. 8-13-10 is the timing chart in the case of a half-word access using an “8-bit bus with fixed wait states, in

synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK

multiplied by four.”

Fig. 8-13-11 is the timing chart in the case of a half-word access using an “8-bit bus with fixed wait states, in

synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK

multiplied by two.”

Fig. 8-13-12 is the timing chart in the case of a half-word access using an “8-bit bus with fixed wait states, in

synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK.”

Note that when writing, WE0 is asserted and the data is output on D7 to 0.

Note: For details on the mode settings, refer to Table 8-9-1, “Mode Settings by the BC External Pins.”

Fig. 8-13-10 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in

Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,

“Description of Registers.”

D7-0

WE0

CSn

MCLK

SYSCLK

REN

A[0]=0 A[0]=1 A[0]=0

A[0]=1

REN

WEN

Read low-

order side

Read high-

order side

Write low-

order side

Write high-

order side

BCE

BCS

BCE

BCS

BCE

BCS

BCE

: Undefined

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Panasonic MN103001G/F01K User Manual Page 153

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